In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip, especially when these components operate at different voltages. Such complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation.
Complete isolation is especially important in the fabrication of analog, power, and mixed signal integrated circuits. In many circuits and applications it may be necessary or desirable to integrate both isolated and non-isolated high-voltage devices on the same chip as other isolated components, with the caveat that high-voltage device fabrication should not degrade the isolation's electrical properties, and that the isolation's fabrication steps should not adversely alter high-voltage device characteristics. There are various ways of doing this.
Conventional CMOS fabricated in P-type substrate material does not facilitate complete isolation of its devices since every P-type well forming the body (back-gate) of NMOS transistors is shorted to the substrate potential, typically the most negative on-chip potential. Epitaxial junction-isolation or epi-JI employs an N-type epitaxial layer grown atop a P-type silicon substrate and separated into electrically isolated tubs by a deep P-type isolation diffusion—one requiring high temperature processes to implement. High temperature processing causes a redistribution of dopant atoms in the substrate and epitaxial layers, causing unwanted tradeoffs and compromises in the manufacturing of dissimilar devices fabricated using one common process. Moreover, the high-temperature diffusions and epitaxy employed in epi-JI processes are generally incompatible with the large wafer diameters and advanced low-temperature processing equipment common in submicron CMOS fabs.
The Benefit of an Isolated Source-Body Short
In high voltage or power devices, there is a distinct performance and survivability advantage to MOS transistors integrating a source-body short over those without a source-body short. Compared to conventional logic and small-signal devices, a power or high voltage device with an integral source-body short has distinct advantage over devices with separate and physically remote source and body contacts.
The need for a source-body short in many power devices is a consequence of their application and power circuit requirements. One way to quickly access the electrical requirements of a power device in a given application is to consider its topological relationship to the load and to its source of power. We herein refer to this relationship as a “switch-load topology”.
In FIGS. 1A and 1B, a power MOSFET connected to ground or a negative potential is connected in series with a load connected to a positive potential or supply Vcc. Since the MOSFET “switch” is connected to ground, we herein topologically refer to it as a low-side switch or LSS, even if it is used as a current source. In FIG. 1A, using a conventional non-isolated CMOS process, circuit 1 includes load 3, an LSS comprising an NMOS 2, and a current sense resistor 4. In such a process, body contact of MOSFET 2 is necessarily shorted to the substrate, i.e. it is grounded.
To measure the voltage across the sense resistor, current sensing requires the source of NMOS 2 should not be shorted to the body and substrate, i.e. VB≠VS. The voltage differential between source and body causes a number of problems. Specifically, any voltage developed across sense resistor 4 increases the source-to-body potential which in turn increases the MOSFET's threshold voltage (due to a phenomenon known as the “body effect”). A high threshold in turn increases on-resistance while lowering saturation current, adversely impacting switch performance. Another undesired effect of disconnecting the source and body is any avalanche or displacement current in drain-to-body diode 5 does not pass through the sense resistor and is therefore not detected. Finally, without a low resistance body contact, snapback breakdown can occur easily.
Using LSS devices with an integral source-body short such as NMOS 12 in circuit 10 of FIG. 1B, drain-to-body diode 15 is anti-parallel to the MOSFET's drain and source terminals (i.e. reverse biased but in parallel), so that any current flowing through load 13 is detected in sense resistor 14 regardless of whether this current flows through the channel of NMOS 12 or through reverse biased diode 15. Because VSB=0 regardless of the source potential, no body effect is manifest, and the transistor's conduction characteristics do not change substantially with current.
The source-body short also improves avalanche-ruggedness by reducing the risk of snapback effects (discussed below), particularly if the source-body short can be distributed uniformly across a large area device rather than shorted together in a single location. Integration of a source body short into a large area NMOS, while common in discrete power devices, requires isolation of the P-type body from the P-type substrate in integrated form, something conventional CMOS cannot offer. Processes offering such isolation are complex to manufacture, often requiring high temperature fabrication steps.
In FIGS. 1C and 1D, a power MOSFET connected to a positive potential or supply Vcc is connected in series with a load connected to ground or a negative potential. Since the MOSFET “switch” is connected to the positive supply, we herein topologically refer to it as a high-side switch or HSS, even if it is used as a current source.
Using a conventional non-isolated CMOS process, circuit 20 in FIG. 1C includes load 23 and a HSS comprising NMOS 22. In such a process, body contact of MOSFET 22 is necessarily shorted to the substrate, i.e. it is grounded. When the NMOS is on and VS increases to a potential approaching Vcc, a large reverse biased potential −VSB develops across diode 25. The resulting body effect causes the threshold of NMOS 22 to increase substantially, making it difficult to provide adequate gate drive to achieve a low on-resistance without damaging the thin gate oxide of NMOS 22.
Using devices with an integral source-body short such as NMOS 32 in circuit 30 of FIG. 1D, the current in load 33 can easily be controlled without the need to counteract threshold variations due to body effect. In such a topology, drain-to-body diode 35 remains anti-parallel to the MOSFET's drain and source terminals (i.e. reverse biased but in parallel), and remains reversed biased under all normal operating conditions. Because VSB=0 regardless of the source potential, no body effect is manifest, and the transistor's conduction characteristics do not change substantially with current. The source-body short also improves avalanche-ruggedness by reducing the risk of snapback effects (discussed below), particularly if the source-body short can be distributed uniformly across a large area device rather than shorted together in a single location. Integration of a source body short into a large area NMOS, while common in discrete power devices, requires isolation of the P-type body from the P-type substrate in integrated form, something conventional CMOS cannot offer. Processes offering such isolation are complex to manufacture, often requiring high temperature fabrication steps.
In FIGS. 1E, 1F and 1G a power MOSFET is employed as a bidirectional switch without either source or drain permanently connected to either a positive or negative supply rail. Since the MOSFET “switch” is not connected to any supply but instead may block current or conduct current in either direction, we herein topologically refer to it as an AC switch, or a “pass transistor”.
Using conventional CMOS fabrication, pass transistor 40 in FIG. 1E comprises NMOS 41 with a grounded body connection and reverse biased source-to-body and drain-to-body diodes 42 and 43, respectively. The terms “source” and “drain” are somewhat arbitrary in pass transistor or AC switch applications since it is often impossible to determine which terminal, the one biased at VS or the one biased at VD, will be more positive at any given instance. Because the voltage across diodes 42 and 43 is large, the body effect can cause significant changes in the threshold, on-resistance, and saturation current of NMOS 41, making it a poor AC switch.
An alternative approach to implementing AC switch requiring at least two NMOS devices with a source-body short is shown in circuit 45 of FIG. 1F, where NMOS transistors 46 and 47 are connected in series with a common source VS such that drain-to-body diodes 48 and 49 are connected back-to-back. In its off state, the gate terminal is biased to the source terminal VS thereby preventing channel conduction. Conduction through the anti-parallel body diodes is also prevented since one of the two diodes remains reversed biased regardless of the polarity applied across the series connected switches.
In its on state, whenever the common gate is biased above the source terminal, AC switch 45 may conduct current in either direction since both transistors are turned on. The resulting AC switch is able to block bi-directionally and conduct bi-directionally. Despite the fact that the voltage Vs floats at a potential between VD1 and VD2, no body effect is manifest since VSB=0, i.e. each transistor has an integral source body short. Such a device can easily be integrated into any process having full isolation or capable of integrating DMOS devices. Without isolation, such a device cannot be integrated monolithically with other components or circuitry. It should also be noted that the devices can be connected with a common drain rather than common source but still need an isolated source-body short.
A disadvantage of AC switch 45 is its high specific on-resistance, i.e. a large RDSA, since the two series connected transistors exhibit additive resistances. If the switches were somehow connected in parallel, then the same area switch would exhibit a resistance one quarter that of the back-to-back approach of switch 45.
One such switch is shown in circuit 50 of FIG. 1G combing a symmetric NMOS device 51 and a body-bias generating (BBG) circuit 52. The purpose of BBG circuit 52 is to bias the body of NMOS 51 to the most negative potential applied across the device, to reverse bias either drain-to-body diode 55 or source-to-body diode 56, depending on whether the VS or VD terminal is more positive. In that way no diode conduction ever occurs and if the gate of the transistor is biased to the body potential, the device is off and will block bi-directionally. Conversely, since the device is symmetric, if the gate is biased “on” the device will conduct bi-directionally. Note that the nomenclature “drain” and “source” are arbitrary and used only to identify the circuit elements.
The BBG circuit shown as an example utilizes cross coupled NMOS transistors 53 and 54 to determine and bias the body potential VB on NMOS 51, but in so doing, they themselves must include a source-body short isolated from the substrate. So while switch 50 does not utilize a DMOS transistor such as the preferred implementation of AC switch 45 does, it still needs isolation to be integrated into an IC with other circuitry.
Suppressing Snapback Breakdown Effects
Aside from the need to integrate NMOS devices with isolated source body shorts, another limitation of conventional CMOS is its inability to prevent undesirable snapback breakdown effects in MOSFET operation, particularly in NMOS transistors.
Snapback breakdown refers to a phenomena leading to negative resistance in a device where for some range of operating conditions an increase in current corresponds to a “decrease” in the voltage sustaining capability of the transistor. Negative resistance is especially problematic in power electronic circuitry, giving rise to excess currents, oscillations and instability, electrical noise, localized heating, thermal runaway and even device destruction.
In power electronics, methods are required to prevent negative resistance at all costs, including using special device construction involving unusual design and process methods, in intentionally degrading or limiting the maximum voltage or current imposed on a device, and by other circuit and application methods. Unless a device is overheating, negative electrical resistance is generally a consequence of either parasitic bipolar conduction, conductivity modulation resulting from impact ionization, or some combination of both.
In FIG. 2A for example, a lightly doped drain NMOS 60 comprising P-type substrate 61, P+ substrate contact 62, N+ drain 64, N− drift region 65, MOS insulated gate 69, and N+ source 63 is biased in its on state with some positive voltage ˜Vcc applied to its drain. Overlaid schematically on the device, is drain diode 59 representing the drain-to-substrate diode current either arising from avalanche, from impact ionization or from junction leakage. The majority-carrier substrate current, or “holes” flowing in P-type substrate 61 exhibits a resistive voltage drop, schematically represented by series-connected RDB and RSB substrate resistances 67 and 68, respectively. Because of substrate resistance, the resulting voltage VB in the bulk substrate located beneath source 63 will rise to a voltage higher than the ground terminal connected to P+ contact 62. If this voltage approaches a few tenths of a volt, N+ region 63 may start to inject electrons, i.e. minority carriers, into substrate 61 which will naturally be attracted by the two-dimensional electric fields in the device to the most positive potential, in this case N+ drain 64. This electron conduction mechanism is represented by parasitic NPN bipolar transistor 66 comprising N+ collector 64, P-type substrate base 61, and N+ emitter 63. Since the voltage sustaining capability of a bipolar transistor is lower than a simple P-N junction diode (because of current gain), the sustaining voltage of NPN 66 is lower than the NMOS itself and the voltage will snapback to a lower value, BVCER—a notation describing the bipolar's collector-to-emitter voltage and having a resistive, non-shorted, base contact.
Another mechanism leading to snapback illustrated in the cross sectional view of FIG. 2B is impact ionization in the drain of the MOSFET. In this case the NMOS is biased to a high-voltage VCC thereby reverse biasing the drain-to-substrate junction comprising N+ drain 64 and P-type substrate 61. The voltage is dropped across a depletion region illustrated by equipotential curves 71 at voltages 0V (substrate), V1, V2, V3, V4 and V5, each curve in increasing magnitude of voltage potential. The N− drift region under such a bias condition depletes, allowing the equipotential lines to cross the junction boundary between the N− drift region and the substrate.
Ideally these equipotential lines should be spaced linearly along the drift region with half the applied voltage being located at the center of the drift region between gate 69 and N+ drain 64. Because of surface charge and other unavoidable surface effects, however, the equipotential lines do not spread themselves uniformly, but instead “bunch up” near the gate edge resulting an a locally higher electric field at the end of the drift region. Even worse, the high electric field is physically located near a region of high current density. In saturation when the device has a high drain potential while conducting current, the main current path indicated by arrow 72, flows under the gate then away from the surface as it approaches the edge of depleted drift region 65. The product of high current density and high electric field results in impact ionization, i.e. local carrier creation, resulting from collisions of fast electrons with the atomic structure of the crystal. The collisions dislodge valence electrons from bonding the atoms together, and convert them into more free conduction electrons which are in turn also accelerated by the locally high electric field.
The resulting impact ionization is herein represented by the concentric contours 73 representing increased generation rates. Since impact ionization creates electron-hole pairs, two undesirable effects result. First the electrons are accelerated to high energies relative to the crystal, i.e. they become energetically “hot”, and may get swept into the gate oxide damaging the dielectric. The second phenomenon is the generated hole current contributes to additional voltage drop across the substrate resistance RSB, exacerbating the NPN snapback effect.
At even higher impact ionization rates and high currents, another phenomenon occurs. In such cases the generated carriers start to alter the local conductivity of the drift region by introducing sufficient additional charge that it begins to alter local space charge neutrality. The extra electrons attract extra holes, which act like an increase in drift doping. The higher effective doping decreases depletion spreading into the N− layer and forces the equipotentials to bunch up even more, essentially increasing the local electric field at the edge of the drift region and further increasing impact ionization. The result is another cause of negative resistance since more impact ionization causes a high local field and contributes to even more current. Moreover, the two negative resistance effects can occur simultaneously, interacting in a complex and even unpredictable way. Regardless of the mechanism, the result is a decrease in the drain voltage that the NMOS can sustain at a given current.
Electrically the phenomenon of snapback is shown in graph 75 of drain current ID versus drain voltage VDS in FIG. 2C. Ideal device breakdown BVDSS shown by curve 76 may be substantially greater than snapback voltage BVCER shown by curve 77, even by a factor of two or more in voltage. If the drain is driven into avalanche at high currents while sustaining voltage BVDSS, it may suddenly collapse back to BVCER, causing the current to increase and destroying the device. If the NMOS is operating as a current source or switching from on to off, the onset of snapback may be exacerbated by increased substrate leakage due to impact ionization. Curves 78, 69, 80, and 81 illustrate the device may not even be useful for operating at any voltage above BVCER.
One reason for the onset of snapback is that the RSB substrate resistance 68 between and beneath N+ source 63 and body contact 62 is too large, especially if the substrate is lightly doped. The other effect is that the parasitic NPN gain is too great since there is not enough base charge in the lightly doped substrate. One obvious way to reduce the NPN transistor's adverse influence is to increase substrate doping, but unfortunately doing so also increases the electric field at the drain leading to even more impact ionization and substrate current.
The snapback effect is sometimes represented schematically by illustrating the parasitic bipolar associated with a MOSFET. For example, circuit 85 in FIG. 2D illustrates NMOS 86 with parasitic NPN 87, and nonlinear emitter to base shorting resistor 88. Similarly a PMOS includes a parasitic PNP, but since PNP gain is much lower than NPN gain, and since hot hole induced impact ionization rates are much lower than electron ionization rates, the snapback phenomenon is less of an issue in a PMOS than in an NMOS.
Conventional DMOS Fabrication
One way to suppress snapback through additional channel doping and lower substrate resistance without increasing the drain electric field is by forming a DMOS field effect transistor. A DMOS, a name where the letter “D” stands for double (and originally for double diffused) is constructed where the channel or body doping under the gate is not uniform, but concentrated or localized near the source side of the gate to avoid adversely increasing electric fields in the vicinity of the drain region. In this way the channel concentration can be adjusted without affecting impact ionization or drain voltage breakdown voltages.
DMOS field effect transistors may be in isolated or non-isolated versions. In conventional technology, the isolated requires the use of epitaxial deposition, generally of N-type epitaxy grown atop a P-type substrate
As shown in FIG. 3A, N-type epitaxial layer 92 is grown atop P-type substrate 91 to form an isolated DMOS device 90, further comprising gate polysilicon 98, gate oxide 99, N+ drain contact 94, N+ source 96, P+ body contact 97 and a P-type “body” or PB region 93 unique to DMOS transistors. The N− drift region 95 is optional and may not be required if the epitaxial doping is sufficient to achieve low on-resistance. The extra N− drift doping may be added to optimize the tradeoff between breakdown and resistance but remains limited by impact ionization effects where the gate juxtaposes the drift region.
In an alternative form N-type epitaxial layer can be replaced by a P-type epitaxial layer or substrate, but then N− drift region 95 is mandatory for device operation. Without an N-type epitaxial layer however, the DMOS is not isolated and has its P-type body electrically shorted to ground, i.e. to the substrate.
Conventional DMOS fabrication is shown in cross sections 100 and 105 in FIGS. 3B and 3C. As shown epitaxial layer 92 is covered by patterned photoresist 101 and implanted by boron at a low energy to form shallow layer 102. The implantation is performed at a low energy, typically between 50 to 100 keV, and nearly perpendicular to the wafer's surface, e.g. only 3 degrees off axis, with limited lateral penetration under gate 98.
The implant is then driven in, i.e. diffused at high temperatures over a long time, to extend the dopant laterally under gate 98 to form junction 93 as shown in FIG. 3C. The diffusion, taking anywhere from 7 to 24 hours, requires high temperatures over 1050° C. and typically 1100° C. or higher, a process incompatible with many modern low-temperature fabrication facilities and large wafer diameters. The progression of the diffusion as shown in FIG. 3C and illustrated by diffusions 106 at times t1, t2 and t3, occurs both laterally and vertically, where the lateral extent is roughly 80% of the vertical junction depth. In the version shown, the body diffusion is self-aligned to the gate since it was implanted after the gate was formed.
If a low temperature process is required, another self aligned fabrication method to form a DMOS device is shown in FIG. 3D. In this technique the body implant is performed at a higher energy, typically at several hundred thousand electron volts, but more importantly at a steep angle, e.g. at 45°, to guarantee the body dopant penetrates laterally under gate 98 to a sufficient extent to fully enclose N+ source 96. The lateral implant method is complex and undesirable for manufacturing since the implant must be performed four times to cover all four gate orientations on a wafer. Rotating the wafer during implantation makes uniform implantation difficult.
Another DMOS fabrication method is to form a non-self aligned DMOS 120 such as shown in FIGS. 3E to 3G. In FIG. 3E, a shallow boron implant 129 is formed in epitaxial layer 122 masked by patterned photoresist 128. The implant is then diffused at high temperatures as shown in FIG. 3F for a long period of time. The P-type region diffuses both vertically and laterally as illustrated by curves 123 representing the P-N junction at increasing times t1, t2, t3 and t4. Finally in FIG. 3G, gate electrode 125 with underlying gate oxide 126 is positioned over the edge of the junction 124 such that the junction at the surface is located between gate edges 127A and 127B. Since it is not self-aligned the relative location of gate 125 and junction 124 is subject to mask misalignment during manufacturing.
In every case described, the process of high temperature diffusion leads to a monotonically decreasing dopant concentration profile of the DMOS body region, with the highest concentration at the wafer's surface. Unfortunately such a profile means the surface electric field is higher than in the bulk away from the surface, not ideal for manufacturing robust avalanche-rugged devices.
Conventional Junction Isolation Fabrication
The high temperature diffusions involved in DMOS body fabrication are further complicated by the steps needed to achieve full electrical isolation of circuitry using epitaxial junction isolation.
In such conventional prior art processes as shown in FIGS. 4A through 4I, a p-type substrate 131 is masked by photoresist 132 and implanted with arsenic or antimony 133, then masked again by photoresist 134 and implanted with boron 135 a shown in FIG. 4C. The implants are then diffused at extremely high temperatures, sometimes as high as 1200° C., and for as long as 24 hours to diffuse the slow moving antimony into the substrate and away from the surface prior to epitaxial growth. During such diffusions, oxide 138 is grown to protect the surface from lateral doping from out-gassing of the buried layers. The oxidation is also used to help define a pattern in the wafer for subsequent mask alignment, since the oxide growth rate over antimony NBL layer 136A will be faster than over boron PBL layer 137A.
After buried layer diffusion, the oxide is stripped off as shown in FIG. 4E and an HCl acid etch is performed in-situ at the beginning of epitaxial growth, thereby removing the top silicon layers to improve adhesion and reduce crystal defects in the epitaxial layer. The result of the epitaxial growth is shown in FIG. 4F where epitaxial layer covers the now expanded NBL region 136B and PBL 137B, both up-diffusing into the epitaxial layer during its high temperature growth.
Next, as shown in FIGS. 4G and 4H. a high dose phosphorus implant 140 is introduced through a mask 141, followed by a high dose boron implant 142 through a photoresist mask 143. After a long high temperature isolation diffusion P-type isolation region 145 connects with a portion of P-type buried layer PBL 137C. Similarly, N-type sinker diffusion 144 connects with buried layer NBL 136C. The depth of the diffusion and the time required depend on the thickness of epitaxial layer 139 and other subsequent high temperature diffusions in the process. High temperature diffusion also causes the buried layers to further expand laterally and up-diffuse to form 137C and 136C larger than their size in the previous processing step, i.e. as 137B and 136B.
Any DMOS body diffusions will also change all the junction depths and the net epitaxial thickness above the buried layers, all making manufacturing processing complex and specific to a particular epitaxial thickness. Since epi thickness determines device voltage ratings, the entire process and the corresponding design rules are all voltage specific.
Adapting Low-Temperature Modular Fabrication to High-Voltage Devices
As described previously, the problem with conventional epitaxial and high-temperature processes and manufacturing methods used to fabricate, isolate, and integrate high-voltage devices is that each high temperature process causes dopant redistribution affecting every high-voltage and low-voltage device. High temperature fabrication also precludes the use of large diameter wafers and modern submicron wafer fabs—fabs capable of high-density transistor integration, large die and high yields at low manufacturing costs.
What is needed is a process for integrating high-voltage and DMOS transistors with fully-isolated floating pockets of low-voltage CMOS, bipolar transistors, diodes, and passive circuit components that eliminates the need for high temperature processing and epitaxy. Ideally, such a manufacturing process should employ “as-implanted” dopant profiles—ones where the final dopant profiles remain substantially unaltered from their original implanted profiles by any subsequent wafer processing steps. Ideally the process should be constructed in a modular architecture where devices may be added or omitted and the corresponding process steps added or removed to the integrated flow without changing the other devices available in the process's device arsenal.